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SII3114CTU 参数 Datasheet PDF下载

SII3114CTU图片预览
型号: SII3114CTU
PDF下载: 下载PDF文件 查看货源
内容描述: PCI串行ATA控制器 [PCI to Serial ATA Controller]
分类和应用: 外围集成电路控制器PC时钟
文件页数/大小: 127 页 / 559 K
品牌: SILICONIMAGE [ Silicon image ]
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SiI3114 PCI to Serial ATA Controller  
Data Sheet  
Silicon Image, Inc.  
Subsystem ID – Subsystem Vendor ID  
Address Offset: 2CH  
Access Type: Read/Write  
Reset Value: 0x3114_1095  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
Subsystem ID  
Subsystem Vendor ID  
This register defines the Subsystem ID fields associated with the PCI bus. The register bits are defined below.  
Bit [31:16]: Subsystem ID (R) – Subsystem ID. The value in this bit field is determined by any one of three  
options:  
1) The default value of 0x3114  
2) Loaded from an external memory device: If an external memory device — flash or EEPROM — is  
present with the correct signature, the Subsystem ID is loaded from that device after reset. See “Auto-  
Initialization” section on page 22 for more information.  
3) System programmable: If Bit 0 of the Configuration register (40H) is set the two bytes are system  
programmable.  
Bit [15:00]: Subsystem Vendor ID (R) – Subsystem Vendor ID. The value in this bit field is determined by  
any one of three options:  
1) The default value of 0x1095  
2) Loaded from an external memory device : If an external memory device – Flash or EEPROM – is  
present with the correct signature, the Subsystem Vendor ID is loaded from that device after reset. See  
“Auto-Initialization” section on page 22 for more information.  
3) System programmable: If Bit 0 of the Configuration register (40H) is set the two bytes are system  
programmable.  
Expansion ROM Base Address  
Address Offset: 30H  
Access Type: Read/Write  
Reset Value: 0x0000_0000  
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00  
Expansion ROM Base Address  
000_0000_0000_0000_000  
This register defines the Expansion ROM base address associated with the PCI bus. The register bits are defined  
below.  
Bit [31:19]: Expansion ROM Base Address (R/W) – Expansion ROM Base Address. This bit field defines  
the upper bits of the Expansion ROM base address.  
Bit [18:01]: Not Used (R). This bit field is hardwired to 00000H. The minimum Expansion ROM address  
range is 512K bytes.  
Bit [00]: Exp ROM Enable (R/W) – Expansion ROM Enable. This bit is set to enable the Expansion ROM  
access.  
© 2007 Silicon Image, Inc.  
31  
SiI-DS-0103-D  
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