SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Capabilities Pointer
Address Offset: 34H
Access Type: Read
Reset Value: 0x0000_0060
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Reserved
Capabilities Pointer
This register defines the link to a list of new capabilities associated with the PCI bus. The register bits are defined
below.
• Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [07:00]: Capabilities Pointer (R) – Capabilities Pointer. This bit field defaults to 60H to define the
address for the 1st entry in a list of PCI Power Management capabilities.
Max Latency – Min Grant – Interrupt Pin – Interrupt Line
Address Offset: 3CH
Access Type: Read/Write
Reset Value: 0x0000_0100
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Max Latency
Min Grant
Interrupt Pin
Interrupt Line
This register defines the various control functions associated with the PCI bus. The register bits are defined
below.
• Bit [31:24]: Max Latency (R) – Maximum Latency. This bit field is hardwired to 00H.
• Bit [23:16]: Min Grant (R) – Minimum Grant. This bit field is hardwired to 00H.
• Bit [15:08]: Interrupt Pin (R) – Interrupt Pin Used. This bit field is hardwired to 01H to indicate that the
SiI3114 uses the INTA# interrupt.
• Bit [07:00]: Interrupt Line (R/W) – Interrupt Line. This bit field is used by the system to indicate interrupt
line routing information. The SiI3114 does not use this information.
Configuration
Address Offset: 40H
Access Type: Read/Write
Reset Value: 0x0000_0000
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Reserved
This register defines the various control functions associated with the PCI bus. The register bits are defined
below.
• Bit [31:02]: Reserved (R). This bit field is hardwired to 00000000H.
SiI-DS-0103-D
32
© 2007 Silicon Image, Inc.
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