SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
PRD Table Address – Channel 0/2
Address Offset: 74H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – Channel 0/2
This register defines the PRD Table Address register for Channel 0/2 in the SiI3114. The register bits are also
mapped to Base Address 4, Offset 04H and Base Address 5, Offset 04H. See “PRD Table Address – Channel X”
section on page 54 for bit definitions.
PCI Bus Master – Channel 1/3
Address Offset: 78H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Reserved
This register defines the PCI bus master register for Channel 1/3 in the SiI3114. The register bits are also
mapped to Base Address 4, Offset 08H, Base Address 5, Offset 08H, and Base Address 5, Offset 18H (Note that
these registers are, however, not identical). See “PCI Bus Master – Channel X” section on page 53 for bit
definitions.
PRD Table Address – Channel 1/3
Address Offset: 7CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – Channel 1/3
This register defines the PRD Table Address register for Channel 1/3 in the SiI3114. The register bits are also
mapped to Base Address 4, Offset 0CH and Base Address 5, Offset 0CH. See “PRD Table Address – Channel X”
section on page 54 for bit definitions.
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
