SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
• Bit [01]: BA5 Ind Acc Ena (R/W) – BA5 Indirect Access Enable. This bit is set to enable indirect access to
BA5 address space using Configuration Space registers C0H and C4H (BA5 Indirect Address and BA5
Indirect Access).
• Bit [00]: PCI Hdr Wr Ena (R/W) – PCI Configuration Header Write Enable. This bit is set to enable write
access to the following registers in the PCI Configuration Header: Device ID (03-02H), PCI Class Code (09-
0BH), Subsystem Vendor ID (2D-2CH), and Subsystem ID (2F-2EH).
Software Data Register
Address Offset: 44H
Access Type: Read/Write
Reset Value: Undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Software Data
This register is used by the software for non-resettable data storage. The contents are unknown on power-up and
are never cleared by any type of reset.
Power Management Capabilities
Address Offset: 60H
Access Type: Read Only
Reset Value: 0x0622_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Auxiliary
Current
PME Support
PPM Rev
Next Item Pointer
Capability ID
This register defines the power management capabilities associated with the PCI bus. The register bits are
defined below.
• Bit [31:27]: PME Support (R) – Power Management Event Support. This bit field is hardwired to 00H to
indicate that the SiI3114 does not support PME.
• Bit [26]: PPM D2 Support (R) – PCI Power Management D2 Support. This bit is hardwired to 1 to indicate
support for the D2 Power Management State.
• Bit [25]: PPM D1 Support (R) – PCI Power Management D1 Support. This bit is hardwired to 1 to indicate
support for the D1 Power Management State.
• Bit [24:22]: Auxiliary Current (R) – Auxiliary Current. This bit field is hardwired to 000B.
• Bit [21]: Dev Special Init (R) – Device Special Initialization. This bit is hardwired to 1 to indicate that the
SiI3114 requires special initialization
• Bit [20]: Reserved (R). This bit is reserved and returns zero on a read.
• Bit [19]: PME Clock (R) – Power Management Event Clock. This bit is hardwired to 0. The SiI3114 does
not support PME.
• Bit [18:16]: PPM Rev (R) – PCI Power Management Revision. This bit field is hardwired to 010B to indicate
compliance with the PCI Power Management Interface Specification revision 1.1.
• Bit [15:08]: Next Item Pointer (R) – PCI Additional Capability Next Item Pointer. This bit field is hardwired to
00H to indicate that there are no additional items on the Capabilities List.
• Bit [07:00]: Capability ID (R) – PCI Additional Capability ID. This bit field is hardwired to 01H to indicate that
this Capabilities List is a PCI Power Management definition.
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
