SiI
1151 PanelLink Receiver
Data Sheet
General DC Specifications
Under normal operating conditions unless otherwise specified.
Table 1. DC Parametric Specifications
Symbol
V
ID
I
PD
I
PDO
Parameter
Differential Input Voltage
Single Ended Amplitude
Power-down Current
Receiver Supply Current
with Outputs Powered Down
Receiver Supply Current
for Active Device
Conditions
Min
75
Typ
Max
1000
5
220
Units
mV
mA
mA
Notes
I
CCR
PD#=LOW, no RXC+
input
ODCK=112MHz,
1 pixel per clock mode
PDO# = LOW
ODCK=112MHz, 0°C
1 pixel per clock mode
PDO#=HIGH
Typ: Typical Pattern
Max: Worst Case Pattern
3
3, 4
220
330
mA
1, 2, 4
Notes
1.
2.
3.
4.
The Typical Pattern contains a gray scale area, checkerboard area, and text.
The Worst Case Pattern consists of a black and white checkerboard pattern; each checker is two pixels wide.
Asserting PD# to LOW disables all internal logic and outputs, including SCDT and clock detect functions. The
inactive input clock accounts for most of the power reduction.
Specified with capacitive load (C
LOAD
) of 10pF on each output pin, and a worst-case TMDS signal swing of 600mV.
SiI-DS-0023-C
4
SILICONIMAGE [ Silicon image ]
