SiI
1151 PanelLink Receiver
Data Sheet
June 2005
General Description
The
SiI
1151 receiver uses PanelLink Digital
technology to support high-resolution displays up to
SXGA (25-112MHz). This receiver supports up to true
color panels (24 bits per pixel, 16M colors) with both
one and two pixels per clock.
All PanelLink products are designed on a scaleable
CMOS architecture, ensuring support for future
performance enhancements while maintaining the
same logical interface. System designers can be
assured that the interface will be stable through a
number of technology and performance generations.
PanelLink Digital technology simplifies PC and display
interface design by resolving many of the system level
issues associated with high-speed mixed signal
design, providing the system designer with a digital
interface solution that is quicker to market and lower in
cost.
Features
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Supports 10 meter cables at SXGA speed
I
2
C port for dynamic optimization of settings to
compensate for long cables and/or poor quality
transmitters
Flexible output drive controls to optimize timings
for all possible configurations
3.3V operation
Time staggered data output for reduced ground
bounce and lower EMI
Sync Detect feature for DVI “Hot Plugging”
ESD tolerant to 5kV (HBM) on all pins
Compliant with DVI 1.0
Guaranteed interoperability with DVI-compliant
transmitters
Low power standby mode; automatic entry into
standby mode with clock detect circuitry
Lead-free universal packaging (see page 39).
SiI
1151 Pin Diagram
ODD 8-bits RED
QO21
74
QO20
QO19
QO18
QO17
QO16
QO15
QO22
75
GND
VCC
ODD 8-bits GREEN
OGND
OVCC
QO14
QO13
QO12
QO11
QO10
QO9
QO8
QO7
QO6
ODD 8-bits BLUE
QO5
QO4
QO3
QO2
73
72
71
70
69
66
65
64
63
62
61
67
60
59
56
55
54
53
52
51
68
57
58
OGND
QO23
OVCC
AGND
RX2+
RX2-
AVCC
AGND
AVCC
RX1+
RX1-
AGND
AVCC
AGND
SIGNAL
PLL
RX0+
RX0-
AGND
RXC+
RXC-
AVCC
EXT_RES
PVCC
PGND
MODE
SCL
(OCK_INV)
DIFFERENTIAL
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
10
11
12
13
14
15
16
17
20
21
22
23
24
25
18
19
6
8
4
5
1
HS_DJTR
2
PD#
3
SDA (ST)
7
9
50
49
48
47
46
45
44
43
QO1
QO0
CONTROLS
HSYNC
VSYNC
DE
OGND
ODCK
OVCC
CTL3
GPO
CTL2
CTL1
GND
VCC
QE23
QE22
EVEN 8-bits RED
QE21
QE20
QE19
QE18
QE17
QE16
OVCC
OGND
QE15
QE14
OUTPUT
CLOCK
SiI
1151
100-Pin
LQFP
(Top View)
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
I2C_MODE#
(STAG_OUT#)
VCC
PDO#
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
QE8
QE9
QE10
QE11
QE12
QE13
PIXS
SCDT
GND
OVCC
OGND
CONFIG. PINS
PWR
MGMT
EVEN 8-bits BLUE
EVEN 8-bits GREEN
SiI-DS-0023-C
SILICONIMAGE [ Silicon image ]
