SiI
1151 PanelLink Receiver
Data Sheet
Functional Description
The
SiI
1151 is a DVI 1.0 compliant PanelLink receiver in a compact package. It provides 24 or 48 bits for data
output, and allows for panel support up to SXGA. Figure 1 shows the functional blocks of the chip.
PIXS
HS_DJTR
OCK_INV
SCL
SDA
EXT_RES
Control Registers
-----------
Termination
and
Equalization
Control
RX2+
RX2-
VCR
Data Recovery
CH2
SYNC2
QE[23:0]
QO[23:0]
RX1+
RX1-
VCR
Data Recovery
CH1
SYNC1
Channel
SYNC
Decoder
Panel
Interface
Logic
ODCK
DE
RX0+
RX0-
VCR
Data Recovery
CH0
SYNC0
HSYNC
VSYNC
SCDT
CTL[3:1]
RXC+
RXC-
PDO#
STAG_OUT#
ST
VCR
PLL
Figure 1. Functional Block Diagram
The PanelLink TMDS core accepts as inputs the three TMDS differential data lines and the differential clock. The
core senses the signals on the link and properly decodes them providing accurate pixel data. The core outputs
the necessary sync signals (HSYNC, VSYNC), clock (ODCK), and a DE signal that goes high when the active
region of the video is present.
The SCDT signal is output when there is active video on the DVI link and the PLL in the TMDS has locked on to
the video. SCDT can be used to trigger external circuitry, indicating that an active video signal is present or used
to place the device in power down when no signal is present (by tying it to PDO#). The EXT_RES component is
used for impedance matching.
SiI-DS-0023-C
2
SILICONIMAGE [ Silicon image ]
