SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.15 FLASH Memory Address – Command + Status
Address Offset: 50H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Memory Address
This register defines the address and command/status register for FLASH memory interface in the SiI 0680A. The register bits
are defined below.
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Bit [31:28]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [27]: Memory Init Done (R) – This bit set indicates that the memory initialization sequence is done. The
memory sequence is activated upon the release of reset.
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Bit [26]: Reserved (R) – This bit is reserved and returns an indeterminate value on a read.
Bit [25]: Mem Access Start (R/W) – Memory Access Start. This bit is set to initiate an operation to FLASH
memory. This bit is cleared by the chip when the operation is complete.
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Bit [24]: Mem Access Type (R/W) – Memory Access Type. This bit is set to define a read operation from
FLASH memory. This bit is cleared to define a write operation to FLASH memory.
Bit [23:19]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [18:00]: Memory Address (R/W). This bit field is programmed with the address for a FLASH memory read or
write access.
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9.7.16 FLASH Memory Data
Address Offset: 54H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Memory Data
This register defines the data register for FLASH memory interface in the SiI 0680A. The system writes to this register for a
write operation to FLASH memory, and reads from this register on a read operation from FLASH memory.
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Bit [31:08]: Reserved (R).
Bit [07:00]: Memory Data (R/W) – FLASH Memory Data. This bit field is used for FLASH write data on a write
operation, and returns the FLASH read data on a read operation.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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