SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.10 PCI Bus Master Byte Count – IDE1
Address Offset: 2CH
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Byte Count High
Byte Count Low
This register defines the byte count register in the PCI bus master logic for IDE Channel #1 in the SiI 0680A. The register bits
are defined below.
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Bit [31]: End of Table (R). This bit set indicates that this is the last entry in the PRD table.
Bit [30:16] Byte Count High (R). This bit field is the PRD entry byte count extension for Large Block Transfer
Mode. Under generic mode, this bit field is reserved and returns zeros on a read.
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Bit [15:00] Byte Count Low (R). This bit field reflects the current DMA1 byte count value.
9.7.11 FIFO Valid Byte Count and Control – IDE0
Address Offset: 40H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
FIFO Valid Byte Count – IDE0
FIFO Wr Req Ctrl – IDE0
FIFO Rd Req Ctrl – IDE0
This register defines the FIFO valid byte count register and PCI bus request control for IDE Channel #0 in the SiI 0680A. The
register bits are defined below.
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Bit [31:25]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [24:16]: FIFO Valid Byte Count – IDE0 (R). This bit field provides the valid byte count for the data FIFO for
IDE Channel #0. A value of 000H indicates empty, while a value of 100H indicates a full FIFO with 256 bytes.
Bit [15:14]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [13:08]: FIFO Wr Req Ctrl – IDE0 (R/W) – FIFO Write Request Control. This bit field defines the FIFO
threshold to assign DMA0 priority when requesting a PCI bus for a write operation. A value of 00H indicates that
DMA0 write request priority is set to 1 whenever the FIFO contains greater than zero DWords, while a value of 3F
H indicates that DMA0 write request priority is set to 1 whenever the FIFO contains greater than 63 Dwords. This
bit field is useful when two DMA channels are competing for accessing PCI bus.
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When the two DMA channels request the PCI bus at the same time, the one with the higher priority will have the
bus when it’s granted to the SiI 0680A. If the two DMA channels have the same priority, the channel that had the
bus last will have the bus when it’s granted to the SiI 0680A.
When one DMA channel is controlling the PCI bus, and the other channel requests the PCI bus, if the channel
currently controlling the PCI bus has the same or higher priority, it remains controlling the bus. However, if the
channel requesting the PCI bus has higher priority, the lower priority channel terminates the PCI transaction,
yielding the bus to the channel with the higher priority.
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Bit [07:06]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [05:00]: FIFO Rd Req Ctrl – IDE0 (R/W) – FIFO Read Request Control. This bit field defines the FIFO
threshold to assign DMA0 priority when requesting a PCI for a read operation. A value of 00H indicates that
DMA0 read request priority is set to 1 whenever the FIFO has greater than zero Dwords available space , while a
value of 3F indicates that DMA0 read request priority is set to 1 whenever the FIFO has greater than 63 Dwords
available space. This bit field is useful when two DMA channels are competing for accessing the PCI bus.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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