Si3220/Si3225
When the THERM pin is connected from the Si3220 or
Si3225 to the Si3200 (indicating the presence of an
Si3200), the resolution of the PTH12 and PSUM RAM
locations is modified from 498 µW/LSB to 1059.6 µW/
LSB. Additionally, the τ
value must be modified
THERMAL
to accommodate the Si3200. For the Si3200, τ
THERMAL
is typically 0.7 s assuming the exposed pad is
connected to the recommended ground plane as stated
in Table 1 on page 4. τ
decreases if the PCB
THERMAL
layout does not provide sufficient thermal conduction.
See “AN58: Si3220/Si3225 Programmer’s Guide” for
details.
Example calculations for PTH12 and PLPF12 in Si3200
mode are shown below:
PTH12 = Si3200 power threshold = 1 W (0x3B0)
PLPF12 = Si3200 thermal LPF pole = 2 (0x0010)
Automatic State Change Based on Power Alarm
If either of the following situations occurs, the device
automatically transitions to the OPEN state:
ꢀ Any of the transistor power alarm thresholds is
exceeded in the case of the discrete transistor
circuit.
ꢀ The total power threshold is exceeded when using
the Si3200.
To provide optimal reliability, the device automatically
transitions into the open state until the user changes the
state manually, independent of whether or not the power
alarm interrupt has been masked. The PQ1E–PQ6E
bits of the IRQEN3 register enable the interrupts for
each transistor power alarm, and the PQ1S to PQ6S
bits of the IRQVEC3 register are set when a power
alarm is triggered in the respective transistor. When
using the Si3200, the PQ1E bit enables the power alarm
interrupt, and the PQ1S bit is set when a Si3200 power
alarm is triggered.
38
Rev. 1.0
SILICONIMAGE [ Silicon image ]
