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SI3225-FQ 参数 Datasheet PDF下载

SI3225-FQ图片预览
型号: SI3225-FQ
PDF下载: 下载PDF文件 查看货源
内容描述: 双PROSLIC®可编程CMOS SLIC / CODEC [DUAL PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC]
分类和应用: 电池电信集成电路
文件页数/大小: 108 页 / 1519 K
品牌: SILICONIMAGE [ Silicon image ]
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Si3220/Si3225  
0 mA  
24 mA  
IRING  
-0 V  
-20 V  
-40 V  
-48 V  
VOCLTH  
VOCHTH  
VOC DELTA  
-80 V  
VRING  
Figure 17. Ground Start VRING RING Behavior  
/I  
Linefeed Calibration  
(V – V  
) and the loop current are also reported.  
RING  
TIP  
For ground start operation, the values reported are  
An internal calibration algorithm corrects for internal and  
external component errors. The calibration is initiated by  
setting the CAL register bit. This bit automatically resets  
upon completion of the calibration cycle.  
A calibration should be executed following system  
powerup. Upon release of the chip reset, the chipset will  
be in the open state, and calibration may be initiated.  
Only one calibration should be necessary if the system  
remains powered up.  
To optimize Dual ProSLIC performance, the calibration  
routine in “AN58: Si3220/Si3225 Programmer’s Guide”  
should be followed.  
Loop Voltage and Current Monitoring  
The Dual ProSLIC chipset continuously monitors the  
TIP and RING voltages and currents. These values are  
available in registers. An internal 8-bit A/D converter  
samples the measured voltages and currents from the  
analog sense circuitry and translates them into the  
digital domain. The A/D updates the samples at an  
800 Hz rate for all inputs except VRNGNG and  
IRNGNG, which are sampled at 8 kHz to provide higher  
resolution for zero-crossing detection in external ringing  
applications. Two derived values, the loop voltage  
V
and the current flowing in the RING lead.  
RING  
Table 20 lists the register set associated with the loop  
monitoring functions.  
The Dual ProSLIC chipsets also include the ability to  
perform loop diagnostic functions as outlined in "Line  
Test and Diagnostics" on page 91.  
Power Monitoring and Power Fault  
Detection  
The Dual ProSLIC line monitoring functions can be  
used to protect the high-voltage circuitry against  
excessive power dissipation and thermal overload  
conditions. The Dual ProSLIC devices can prevent  
thermal overloads by regulating the total power inside  
the Si3200 or in each of the external bipolar transistors  
(if using a discrete linefeed circuit). The DSP engine  
performs all power calculations and provides the ability  
to automatically transition the device into the OPEN  
state and generate a power alarm interrupt when  
excessive power is detected. Table 21 on page 39  
describes the register and RAM locations used for  
power monitoring.  
Rev. 1.0  
35