Si3056
Si3018/19/10
Master
Serial Mode 0
Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1
Slave 1
Serial Mode 2
Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1
Primary Frame (Data)
Secondary Frame (Control)
128 SCLKs
128 SCLKs
16 SCLKs
Master FSYNC
Master FSD/
Slave1 FSYNC
SDI [0]
SDI [15..1]
1
1
Master
Master
Slave1
Slave1
Master
Slave1
SD0 [0]
SD0 [15..1]
1
0
Master
Master
Slave1
Slave1
Master
Slave1
Comments
Primary frames with secondary frame requested via SDI[0] = 1
Figure 34. Daisy Chaining with Framed FSYNC and Framed FSD
MCLK
Host
SCLK
Si3056
MCLK
SCLK
SDI
SDO
SDO
SDI
FSYNC
FSYNC
INT0
FC/RGDT
RGDT/FSD/M1
VCC
M0
47 kΩ
47 kΩ
47 kΩ
+5 V
47 kΩ
Si3000
SCLK
MCLK
FSYNC
SDI
SDO
Voice
Codec
Figure 35. Typical Connection for Master/Slave Operation (e.g., Data/Fax/Voice Modem)
46
Rev. 1.05
SILICON [ SILICON ]
