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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,  
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be  
set up by the software prior to receiving the byte when hardware ACK generation is enabled.  
Writing a 1 to the ACK bit generates an ACK; writing a 0 generates a NACK. Software should write a 0 to  
the ACK bit for the last data transfer, to transmit a NACK. The interface exits Master Receiver Mode after  
the STO bit is set and a STOP is generated. The interface will switch to Master Transmitter Mode if  
SMB0DAT is written while an active Master Receiver. Figure 24.6 shows a typical master read sequence.  
Two received data bytes are shown, though any number of bytes may be received. Notice that the ‘data  
byte transferred’ interrupts occur at different places in the sequence, depending on whether hardware ACK  
generation is enabled. The interrupt occurs before the ACK with hardware ACK generation disabled, and  
after the ACK when hardware ACK generation is enabled.  
Interrupts with Hardware ACK Enabled (EHACK = 1)  
S
SLA  
R
A
Data Byte  
A
Data Byte  
N
P
Interrupts with Hardware ACK Disabled (EHACK = 0)  
S = START  
P = STOP  
A = ACK  
Received by SMBus  
Interface  
N = NACK  
R = READ  
SLA = Slave Address  
Transmitted by  
SMBus Interface  
Figure 24.6. Typical Master Read Sequence  
24.5.3. Write Sequence (Slave)  
During a write sequence, an SMBus master writes data to a slave device. The slave in this transfer will be  
a receiver during the address byte, and a receiver during all data bytes. When slave events are enabled  
(INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and direc-  
tion bit (WRITE in this case) is received. If hardware ACK generation is disabled, upon entering Slave  
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the  
received slave address with an ACK, or ignore the received slave address with a NACK. If hardware ACK  
generation is enabled, the hardware will apply the ACK for a slave address which matches the criteria set  
up by SMB0ADR and SMB0ADM. The interrupt will occur after the ACK cycle.  
If the received slave address is ignored (by software or hardware), slave interrupts will be inhibited until the  
next START is detected. If the received slave address is acknowledged, zero or more data bytes are  
received.  
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each  
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.  
With hardware ACK generation enabled, the SMBus hardware will automatically generate the ACK/NACK,  
and then post the interrupt. It is important to note that the appropriate ACK or NACK value should be  
set up by the software prior to receiving the byte when hardware ACK generation is enabled.  
The interface exits Slave Receiver Mode after receiving a STOP. Note that the interface will switch to Slave  
Transmitter Mode if SMB0DAT is written while an active Slave Receiver. Figure 24.7 shows a typical slave  
write sequence. Two received data bytes are shown, though any number of bytes may be received. Notice  
Rev. 1.0  
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