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SI1002-C-GM 参数 Datasheet PDF下载

SI1002-C-GM图片预览
型号: SI1002-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
24.5. SMBus Transfer Modes  
The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be  
operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or  
Slave Receiver. The SMBus interface enters Master Mode any time a START is generated, and remains in  
Master Mode until it loses an arbitration or generates a STOP. An SMBus interrupt is generated at the end  
of all SMBus byte frames. Note that the position of the ACK interrupt when operating as a receiver  
depends on whether hardware ACK generation is enabled. As a receiver, the interrupt for an ACK occurs  
before the ACK with hardware ACK generation disabled, and after the ACK when hardware ACK genera-  
tion is enabled. As a transmitter, interrupts occur after the ACK, regardless of whether hardware ACK gen-  
eration is enabled or not.  
24.5.1. Write Sequence (Master)  
During a write sequence, an SMBus master writes data to a slave device. The master in this transfer will be  
a transmitter during the address byte, and a transmitter during all data bytes. The SMBus interface gener-  
ates the START condition and transmits the first byte containing the address of the target slave and the  
data direction bit. In this case the data direction bit (R/W) will be logic 0 (WRITE). The master then trans-  
mits one or more bytes of serial data. After each byte is transmitted, an acknowledge bit is generated by  
the slave. The transfer is ended when the STO bit is set and a STOP is generated. Note that the interface  
will switch to Master Receiver Mode if SMB0DAT is not written following a Master Transmitter interrupt.  
Figure 24.5 shows a typical master write sequence. Two transmit data bytes are shown, though any num-  
ber of bytes may be transmitted. Notice that all of the ‘data byte transferred’ interrupts occur after the ACK  
cycle in this mode, regardless of whether hardware ACK generation is enabled.  
Interrupts with Hardware ACK Enabled (EHACK = 1)  
S
SLA  
W
A
Data Byte  
A
Data Byte  
A
P
Interrupts with Hardware ACK Disabled (EHACK = 0)  
S = START  
P = STOP  
A = ACK  
Received by SMBus  
Interface  
W = WRITE  
Transmitted by  
SLA = Slave Address  
SMBus Interface  
Figure 24.5. Typical Master Write Sequence  
24.5.2. Read Sequence (Master)  
During a read sequence, an SMBus master reads data from a slave device. The master in this transfer will  
be a transmitter during the address byte, and a receiver during all data bytes. The SMBus interface gener-  
ates the START condition and transmits the first byte containing the address of the target slave and the  
data direction bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then  
received from the slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more  
bytes of serial data.  
If hardware ACK generation is disabled, the ACKRQ is set to 1 and an interrupt is generated after each  
received byte. Software must write the ACK bit at that time to ACK or NACK the received byte.  
302  
Rev. 1.0