Si1000/1/2/3/4/5
24.4.4. Limitations for Hardware Acknowledge Feature
In some system management bus (SMBus) configurations, the Hardware Acknowledge mechanism of the
SMBus peripheral can cause incorrect or undesired behavior. The Hardware Acknowledge mechanism is
enabled when the EHACK bit (SMB0ADM.0) is set to logic 1.
The configurations to which these limitations do not apply are as follows:
a. All SMBus configurations when Hardware Acknowledge is disabled.
b. All single-master/single-slave SMBus configurations when Hardware Acknowledge is enabled
and the MCU is operating as a master or slave.
c. All multi-master/single-slave SMBus configurations when Hardware Acknowledge is enabled
and the MCU is operating as a slave.
d. All single-master/multi-slave SMBus configurations when Hardware Acknowledge is enabled
and the MCU is operating as a master.
These limitations only apply to the following configurations:
a. All multi-slave SMBus configurations when Hardware Acknowledge is enabled and the MCU is
operating as a slave.
b. All multi-master SMBus configurations when Hardware Acknowledge is enabled and the MCU
is operating as a master.
The following issues are present when operating as a slave in a multi-slave SMBus configuration:
a. When Hardware Acknowledge is enabled and SDA setup and hold times are not extended
(EXTHOLD = 0 in the SMB0CF register), the SMBus hardware will always generate an SMBus
interrupt following the ACK/NACK cycle of any slave address transmission on the bus, whether
or not the address matches the conditions of SMB0ADR and SMB0MASK. The expected
behavior is that an interrupt is only generated when the address matches.
b. When Hardware Acknowledge is enabled and SDA setup and hold times are extended
(EXTHOLD = 1 in the SMB0CF register), the SMBus hardware will only generate an SMBus
interrupt as expected when the slave address transmission on the bus matches the conditions of
SMB0ADR and SMB0MASK. However, in this mode, the Start bit (STA) will be incorrectly
cleared on reception of a slave address before software vectors to the interrupt service routine.
c. When Hardware Acknowledge is enabled and the ACK bit (SMB0CN.1) is set to 1, an
unaddressed slave may cause interference on the SMBus by driving SDA low during an ACK
cycle. The ACK bit of the unaddressed slave may be set to 1 if any device on the bus generates
an ACK.
Impact:
a. Once the CPU enters the interrupt service routine, SCL will be asserted low until SI is cleared,
causing the clock to be stretched when the MCU is not being addressed. This may limit the
maximum speed of the SMBus if the master supports SCL clock stretching. Incompliant SMBus
masters that do not support SCL clock stretching will not recognize that the clock is being
stretched. If the CPU issues a write to SMB0DAT, it will have no effect on the bus. No data
collisions will occur.
b. Once the hardware has matched an address and entered the interrupt service routine, the
firmware will not be able to use the Start bit to distinguish between the reception of an address
byte versus the reception of a data byte. However, the hardware will still correctly acknowledge
the address byte (SLA+R/W).
c. The SMBus master and the addressed slave are prevented from generating a NACK by the
unaddressed slave because it is holding SDA low during the ACK cycle. There is a potential for
the SMBus to lock up.
Rev. 1.0
299
SILICON [ SILICON ]
