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SI1005 参数 Datasheet PDF下载

SI1005图片预览
型号: SI1005
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
5.2.3. Burst Mode  
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between conver-  
sions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or  
64 using an internal Burst Mode clock (approximately 20 MHz), then re-enters a low power state. Since the  
Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions then enter a  
low power state within a single system clock cycle, even if the system clock is slow (e.g. 32.768 kHz), or  
suspended.  
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0  
idle power state (i.e., the state ADC0 enters when not tracking or performing conversions). If AD0EN is set  
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after  
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered  
down, it will automatically power up and wait the programmable Power-Up Time controlled by the  
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.3 shows an exam-  
ple of Burst Mode Operation with a slow system clock and a repeat count of 4.  
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat  
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,  
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have  
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and  
less-than registers until “repeat count” conversions have been accumulated.  
In Burst Mode, tracking is determined by the settings in AD0PWR and AD0TK. The default settings for  
these registers will work in most applications without modification; however, settling time requirements may  
need adjustment in some applications. Refer to “5.2.4. Settling Time Requirements” on page 79 for more  
details.  
Notes:  
Setting AD0TM to 1 will insert an additional 3 SAR clocks of tracking before each conversion,  
regardless of the settings of AD0PWR and AD0TK.  
When using Burst Mode, care must be taken to issue a convert start signal no faster than once every  
four SYSCLK periods. This includes external convert start signals.  
System Clock  
Convert Start  
AD0TM = 1  
AD0EN = 0  
Powered  
Down  
Power-Up  
and Track  
T
3
T
3
T
3
T
3
Powered  
Down  
Power-Up  
and Track  
C
T
C
T
C
T
C
T
T
C..  
C..  
AD0TM = 0  
AD0EN = 0  
Powered  
Down  
Power-Up  
and Track  
Powered  
Down  
Power-Up  
and Track  
C
T
C
T
C
T
C
AD0PW R  
AD0TK  
T = Tracking set by AD0TK  
T3 = Tracking set by AD0TM (3 SAR clocks)  
C = Converting  
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4  
78  
Rev. 1.0