Si1000/1/2/3/4/5
5.2.5. Gain Setting
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by V . In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is V
x 2.
REF
REF
The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small V
volt-
REF
age, or to measure input voltages that are between V
trolled by the AMP0GN bit in register ADC0CF.
and V . Gain settings for the ADC are con-
DD
REF
5.3. 8-Bit Mode
Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the
8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles
than a 10-bit conversion. This can result in an overall lower power consumption since the system can
spend more time in a low power mode. The two LSBs of a conversion are always 00 in this mode, and the
ADC0L register will always read back 0x00.
80
Rev. 1.0
SILICON [ SILICON ]
