Si1000/1/2/3/4/5
5.2. Modes of Operation
ADC0 has a maximum conversion speed of 300 ksps. The ADC0 conversion clock (SARCLK) is a divided
version of the system clock when Burst Mode is disabled (BURSTEN = 0), or a divided version of the low
power oscillator when Burst Mode is enabled (BURSEN = 1). The clock divide value is determined by the
AD0SC bits in the ADC0CF register.
5.2.1. Starting a Conversion
A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM2–0) in register ADC0CN. Conversions may be initiated by one of the fol-
lowing:
1. Writing a 1 to the AD0BUSY bit of register ADC0CN
2. A Timer 0 overflow (i.e., timed continuous conversions)
3. A Timer 2 overflow
4. A Timer 3 overflow
5. A rising edge on the CNVSTR input signal (pin P0.6)
Writing a 1 to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-
demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is
complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt
flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)
should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT
is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte over-
flows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode.
See “27. Timers” on page 330 for timer configuration.
Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the
CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital
Crossbar. To configure the Crossbar to skip P0.6, set to 1 Bit 6 in register P0SKIP. See “21. Port Input/Out-
put” on page 207 for details on Port I/O configuration.
Important Note: When operating the device in one-cell mode, there is an option available to automatically
synchronize the start of conversion with the quietest portion of the dc-dc converter switching cycle. Activat-
ing this option may help to reduce interference from internal or external power supply noise generated by
the dc-dc converter. Asserting this bit will hold off the start of an ADC conversion initiated by any of the
methods described above until the ADC receives a synchronizing signal from the dc-dc converter. The
delay in initiation of the conversion can be as much as one cycle of the dc-dc converter clock, which is
625 ns at the minimum dc-dc clock frequency of 1.6 MHz. For rev C and later C8051F93x-92x devices, the
synchronization feature also causes the dc-dc converter clock to be used as the ADC0 conversion clock.
The maximum conversion rate will be limited to approximately 170 ksps at the maximum dc-dc converter
clock rate of 3.2 MHz. In this mode, the ADC0 SAR Conversion Clock Divider must be set to 1 by setting
AD0SC[4:0] = 00000b in SFR register ADC0CF. To provide additional flexibility in minimizing noise, the
ADC0 conversion clock provided by the dc-dc converter can be inverted by setting the AD0CKINV bit in the
DC0CF register. For additional information on the synchronization feature, see the description of the SYNC
bit in “SFR Definition 16.1. DC0CN: DC-DC Converter Control” on page 171 and the description of the
AD0CKINV bit in “SFR Definition 16.2. DC0CF: DC-DC Converter Configuration” on page 172. This bit
must be set to 0 in two-cell mode for the ADC to operate.
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SILICON [ SILICON ]
