Si1000/1/2/3/4/5
SFR Definition 12.5. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
3
2
1
0
ESPI1
ERTC0F
EMAT
EWARN
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = All Pages;SFR Address = 0xE7
Bit
7:4
3
Name
Function
Read = 0000b. Write = Don’t care.
Unused
ESPI1 Enable Serial Peripheral Interface (SPI1) Interrupt.
This bit sets the masking of the SPI1 interrupts.
0: Disable all SPI1 interrupts.
1: Enable interrupt requests generated by SPI1.
2
1
0
ERTC0F Enable SmaRTClock Oscillator Fail Interrupt.
This bit sets the masking of the SmaRTClock Alarm interrupt.
0: Disable SmaRTClock Alarm interrupts.
1: Enable interrupt requests generated by SmaRTClock Alarm.
EMAT Enable Port Match Interrupts.
This bit sets the masking of the Port Match Event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
EWARN Enable VDD_MCU Supply Monitor Early Warning Interrupt.
This bit sets the masking of the VDD_MCU Supply Monitor Early Warning interrupt.
0: Disable the VDD_MCU Supply Monitor Early Warning interrupt.
1: Enable interrupt requests generated by VDD_MCU Supply Monitor.
Rev. 1.0
137
SILICON [ SILICON ]
