Si1000/1/2/3/4/5
SFR Definition 12.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
5
4
3
2
1
0
PSPI1
PRTC0F
PMAT
PWARN
Name
Type
Reset
R
0
R
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Page = All Pages; SFR Address = 0xF7
Bit
7:4
3
Name
Function
Unused
Read = 0000b. Write = Don’t care.
PSPI1 Serial Peripheral Interface (SPI1) Interrupt Priority Control.
This bit sets the priority of the SPI1 interrupt.
0: SP1 interrupt set to low priority level.
1: SPI1 interrupt set to high priority level.
2
1
0
PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
PMAT Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
PWARN VDD_MCU Supply Monitor Early Warning Interrupt Priority Control.
This bit sets the priority of the VDD_MCU Supply Monitor Early Warning interrupt.
0: VDD_MCU Supply Monitor Early Warning interrupt set to low priority level.
1: VDD_MCU Supply Monitor Early Warning interrupt set to high priority level.
138
Rev. 1.0
SILICON [ SILICON ]
