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SI1005-C-GM 参数 Datasheet PDF下载

SI1005-C-GM图片预览
型号: SI1005-C-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
分类和应用:
文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
SFR Definition 12.4. EIP1: Extended Interrupt Priority 1  
Bit  
7
6
5
4
3
2
1
0
PT3  
PCP1  
PCP0  
PPCA0  
PADC0  
PWADC0 PRTC0A  
PSMB0  
Name  
Type  
Reset  
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
R/W  
0
SFR Page = All Pages; SFR Address = 0xF6  
Bit  
Name  
Function  
7
PT3  
Timer 3 Interrupt Priority Control.  
This bit sets the priority of the Timer 3 interrupt.  
0: Timer 3 interrupts set to low priority level.  
1: Timer 3 interrupts set to high priority level.  
6
5
4
3
2
1
0
PCP1  
PCP0  
Comparator1 (CP1) Interrupt Priority Control.  
This bit sets the priority of the CP1 interrupt.  
0: CP1 interrupt set to low priority level.  
1: CP1 interrupt set to high priority level.  
Comparator0 (CP0) Interrupt Priority Control.  
This bit sets the priority of the CP0 interrupt.  
0: CP0 interrupt set to low priority level.  
1: CP0 interrupt set to high priority level.  
PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.  
This bit sets the priority of the PCA0 interrupt.  
0: PCA0 interrupt set to low priority level.  
1: PCA0 interrupt set to high priority level.  
PADC0 ADC0 Conversion Complete Interrupt Priority Control.  
This bit sets the priority of the ADC0 Conversion Complete interrupt.  
0: ADC0 Conversion Complete interrupt set to low priority level.  
1: ADC0 Conversion Complete interrupt set to high priority level.  
PWADC0 ADC0 Window Comparator Interrupt Priority Control.  
This bit sets the priority of the ADC0 Window interrupt.  
0: ADC0 Window interrupt set to low priority level.  
1: ADC0 Window interrupt set to high priority level.  
PRTC0A SmaRTClock Alarm Interrupt Priority Control.  
This bit sets the priority of the SmaRTClock Alarm interrupt.  
0: SmaRTClock Alarm interrupt set to low priority level.  
1: SmaRTClock Alarm interrupt set to high priority level.  
PSMB0 SMBus (SMB0) Interrupt Priority Control.  
This bit sets the priority of the SMB0 interrupt.  
0: SMB0 interrupt set to low priority level.  
1: SMB0 interrupt set to high priority level.  
136  
Rev. 1.0