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SI1005-C-GM 参数 Datasheet PDF下载

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型号: SI1005-C-GM
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内容描述: 超低功耗, 64/32 KB , 10位ADC, MCU ,集成了240-960兆赫的EZRadioPRO收发器 [Ultra Low Power, 64/32 kB, 10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver]
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文件页数/大小: 376 页 / 2369 K
品牌: SILICON [ SILICON ]
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Si1000/1/2/3/4/5  
13. Flash Memory  
On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The  
Flash memory can be programmed in-system through the C2 interface or by software using the MOVX  
write instruction. Once cleared to logic 0, a Flash bit must be erased to set it back to logic 1. Flash bytes  
would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations are  
automatically timed by hardware for proper execution; data polling to determine the end of the write/erase  
operations is not required. Code execution is stalled during Flash write/erase operations. Refer to  
Table 4.6 for complete Flash memory electrical characteristics.  
13.1. Programming The Flash Memory  
The simplest means of programming the Flash memory is through the C2 interface using programming  
tools provided by Silicon Laboratories or a third party vendor. This is the only means for programming a  
non-initialized device. For details on the C2 commands to program Flash memory, see Section “29. C2  
Interface” on page 371.  
The Flash memory can be programmed by software using the MOVX write instruction with the address and  
data byte to be programmed provided as normal operands. Before programming Flash memory using  
MOVX, Flash programming operations must be enabled by: (1) setting the PSWE Program Store Write  
Enable bit (PSCTL.0) to logic 1 (this directs the MOVX writes to target Flash memory); and (2) Writing the  
Flash key codes in sequence to the Flash Lock register (FLKEY). The PSWE bit remains set until cleared  
by software. For detailed guidelines on programming Flash from firmware, please see Section “13.5. Flash  
Write and Erase Guidelines” on page 145.  
To ensure the integrity of the Flash contents, the on-chip VDD Monitor must be enabled and enabled as a  
reset source in any system that includes code that writes and/or erases Flash memory from software. Fur-  
thermore, there should be no delay between enabling the V Monitor and enabling the V Monitor as a  
DD  
DD  
reset source. Any attempt to write or erase Flash memory while the V  
Monitor is disabled, or not  
DD  
enabled as a reset source, will cause a Flash Error device reset.  
13.1.1. Flash Lock and Key Functions  
Flash writes and erases by user software are protected with a lock and key function. The Flash Lock and  
Key Register (FLKEY) must be written with the correct key codes, in sequence, before Flash operations  
may be performed. The key codes are: 0xA5, 0xF1. The timing does not matter, but the codes must be  
written in order. If the key codes are written out of order, or the wrong codes are written, Flash writes and  
erases will be disabled until the next system reset. Flash writes and erases will also be disabled if a Flash  
write or erase is attempted before the key codes have been written properly. The Flash lock resets after  
each write or erase; the key codes must be written again before a following Flash operation can be per-  
formed. The FLKEY register is detailed in SFR Definition 13.2.  
Rev. 1.0  
141  
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