C8051F52x-53x
Table 5.2. ADC0 Electrical Characteristics (V = 2.1 V, V
= 1.5 V)
DD
VDD = 2.1 V, VREF = 1.5 V (REFSL = 0), –40 to +125 °C unless otherwise specified
REF
Parameter
DC Accuracy
Conditions
Min
Typ
Max
Units
Resolution
12
—
bits
C8051F52x/C8051F53x
devices
Integral Nonlinearity
—
±1
LSB
Differential Nonlinearity
Offset Error
Guaranteed Monotonic
—
—
—
—
±1
±1
±1
—
—
LSB
LSB
LSB
Full Scale Error
Dynamic Performance (10 kHz sine-wave Single-ended input, 0 to 1 dB below Full Scale, 200 ksps)
C8051F52x/C8051F53x
devices
Signal-to-Noise Plus Distortion
68
—
—
dB
th
Total Harmonic Distortion
Spurious-Free Dynamic Range
Conversion Rate
SAR Conversion Clock
Conversion Time in SAR Clocks
Track/Hold Acquisition Time
Throughput Rate
—
—
76
91
—
—
dB
dB
Up to the 5 harmonic
—
—
1
—
13
—
—
10
—
MHz
clocks
µs
Note 1
Note 2
—
—
200
ksps
Analog Inputs
Input Voltage Range
Input Capacitance
Temperature Sensor
Linearity
0
—
4.6 or 2.3
—
V
—
12
pF
Notes 3, 4
—
—
—
0.1
2.89
888
—
—
—
°C
µV / °C
mV
Gain
Notes 3, 4
Offset
Notes 3, 4 (Temp = 0 °C)
Power Specifications
Power Supply Current (V sup-
DD
Operating Mode, 200 ksps
—
840
—
µA
plied to ADC0)
Burst Mode (Idle)
Power-On Time
Power Supply Rejection
Notes:
—
TBD
—
880
—
—
—
—
µA
µs
TBD
mV/V
1. An additional 2 FCLK cycles are required to start and complete a conversion.
2. Additional tracking time may be required depending on the output impedance connected to the ADC input.
See Section “5.3.6. Settling Time Requirements” on page 48.
3. Represents one standard deviation from the mean.
4. Includes ADC offset, gain, and linearity variations.
Rev. 0.3
61
SILICON [ SILICON ]
