C8051F52x-53x
20.3.1. Watchdog Timer Operation
While the WDT is enabled:
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•
•
•
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PCA counter is forced on.
Writes to PCA0L and PCA0H are not allowed.
PCA clock source bits (CPS2-CPS0) are frozen.
PCA Idle control bit (CIDL) is frozen.
Module 2 is forced into software timer mode.
Writes to the Module 2 mode register (PCA0CPM2) are disabled.
While the WDT is enabled, writes to the CR bit will not change the PCA counter state; the counter will run
until the WDT is disabled. The PCA counter run control (CR) will read zero if the WDT is enabled but user
software has not enabled the PCA counter. If a match occurs between PCA0CPH2 and PCA0H while the
WDT is enabled, a reset will be generated. To prevent a WDT reset, the WDT may be updated with a write
of any value to PCA0CPH2. Upon a PCA0CPH2 write, PCA0H plus the offset held in PCA0CPL2 is loaded
into PCA0CPH2 (See Figure 20.10).
PCA0MD
C W W C C C E
I D D P P P C
PCA0CPH_
D T L S S S F
L E C 2 1 0
K
8-bit
Comparator
Match
Reset
Enable
PCA0L Overflow
PCA0CPL_
8-bit Adder
PCA0H
Adder
Enable
Write to
PCA0CPH5
Figure 20.10. PCA Module 2 with Watchdog Timer Enabled
208
Rev. 0.3
SILICON [ SILICON ]
