C8051F52x-53x
SFR Definition 14.1. XBR0: Port I/O Crossbar Register 0
R/W
-
R/W
-
R/W
CP0AE
Bit5
R/W
CP0E
Bit4
R/W
SYSCKE
Bit3
R/W
LINE
Bit2
R/W
SPI0E
Bit1
R/W
Reset Value
URT0E 00000000
Bit0
Bit7
Bit6
SFR Address:
0xE1
Bit7–6: RESERVED. Read = 0b; Must write 0b.
Bit5:
Bit4:
Bit3:
CP0AE: Comparator0 Asynchronous Output Enable
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
CP0E: Comparator0 Output Enable
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
SYSCKE: /SYSCLK Output Enable
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
LINE. Lin Output Enable
Bit2:
Bit1:
SPI0E: SPI I/O Enable
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO pins.
URT0E: UART I/O Output Enable
Bit0:
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins (P0.3 and P0.4) or (P0.4 and P0.5).
Note:Please refer to Section “21. Revision Specific Behavior” on page 215.
124
Rev. 0.3
SILICON [ SILICON ]
