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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
SFR Definition 6.5. ADC0H: ADC0 Data Word MSB  
Bit  
7
6
5
4
3
2
1
0
ADC0H[7:0]  
R/W  
Name  
Type  
Reset  
0
0
0
0
0
0
0
0
SFR Address = 0xBE; SFR Page = 0x00  
Bit Name  
7:0 ADC0H[7:0] ADC0 Data Word High-Order Bits.  
For AD0LJST = 0 and AD0RPT as follows:  
Function  
00: Bits 3–0 are the upper 4 bits of the 12-bit result. Bits 7–4 are 0000b.  
01: Bits 4–0 are the upper 5 bits of the 14-bit result. Bits 7–5 are 000b.  
10: Bits 5–0 are the upper 6 bits of the 15-bit result. Bits 7–6 are 00b.  
11: Bits 7–0 are the upper 8 bits of the 16-bit result.  
For AD0LJST = 1 (AD0RPT must be 00): Bits 7–0 are the most-significant bits of the  
ADC0 12-bit result.  
SFR Definition 6.6. ADC0L: ADC0 Data Word LSB  
Bit  
7
6
5
4
3
2
1
0
ADC0L[7:0]  
R/W  
Name  
Type  
Reset  
0
0
0
0
0
0
0
0
SFR Address = 0xBD; SFR Page = 0x00  
Bit Name  
7:0 ADC0L[7:0] ADC0 Data Word Low-Order Bits.  
Function  
For AD0LJST = 0: Bits 7–0 are the lower 8 bits of the ADC0 Accumulated Result.  
For AD0LJST = 1 (AD0RPT must be '00'): Bits 74 are the lower 4 bits of the 12-bit  
result. Bits 30 are 0000b.  
64  
Rev. 1.1  
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