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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
6.3.2. Setting the Gain Value  
The three programmable gain registers are accessed indirectly using the ADC0H and ADC0L registers  
when the GAINEN bit (ADC0CF.0) bit is set. ADC0H acts as the address register, and ADC0L is the data  
register. The programmable gain registers can only be written to and cannot be read. See Gain Register  
Definition 6.1, Gain Register Definition 6.2, and Gain Register Definition 6.3 for more information.  
The gain is programmed using the following steps:  
1. Set the GAINEN bit (ADC0CF.0)  
2. Load the ADC0H with the ADC0GNH, ADC0GNL, or ADC0GNA address.  
3. Load ADC0L with the desired value for the selected gain register.  
4. Reset the GAINEN bit (ADC0CF.0)  
Notes:  
1. An ADC conversion should not be performed while the GAINEN bit is set.  
2. Even with gain enabled, the maximum input voltage must be less than VREGIN and the maximum  
voltage of the signal after gain must be less than or equal to VREF  
.
In code, changing the value to 0.44 gain from the previous example looks like:  
// in ‘C’:  
ADC0CF |= 0x01;  
ADC0H = 0x04;  
ADC0L = 0x6C;  
ADC0H = 0x07;  
ADC0L = 0xA0;  
ADC0H = 0x08;  
ADC0L = 0x01;  
ADC0CF &= ~0x01;  
// GAINEN = 1  
// Load the ADC0GNH address  
// Load the upper byte of 0x6CA to ADC0GNH  
// Load the ADC0GNL address  
// Load the lower nibble of 0x6CA to ADC0GNL  
// Load the ADC0GNA address  
// Set the GAINADD bit  
// GAINEN = 0  
; in assembly  
ORL ADC0CF,#01H  
MOV ADC0H,#04H  
MOV ADC0L,#06CH  
MOV ADC0H,#07H  
MOV ADC0L,#0A0H  
MOV ADC0H,#08H  
MOV ADC0L,#01H  
ANL ADC0CF,#0FEH  
; GAINEN = 1  
; Load the ADC0GNH address  
; Load the upper byte of 0x6CA to ADC0GNH  
; Load the ADC0GNL address  
; Load the lower nibble of 0x6CA to ADC0GNL  
; Load the ADC0GNA address  
; Set the GAINADD bit  
; GAINEN = 0  
60  
Rev. 1.1  
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