C8051F50x-F51x
SFR Definition 6.4. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
AD0SC[4:0]
AD0RPT[1:0]
R/W R/W
GAINEN
Name
Type
Reset
R/W
1
R/W
0
1
1
1
1
0
0
SFR Address = 0xBC; SFR Page = 0x00
Bit Name
Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table
BURSTEN = 0: FCLK is the current system clock
BURSTEN = 1: FLCLK is a maximum of 30 Mhz, independent of the current system
clock..
FCLK
AD0SC = -------------------- – 1
CLKSAR
Note: Round up the result of the calculation for AD0SC
2:1 A0RPT[1:0] ADC0 Repeat Count
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A con-
vert start is required for each conversion unless Burst Mode is enabled. In Burst
Mode, a single convert start can initiate multiple self-timed conversions. Results in
both modes are accumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are
set to a value other than '00', the AD0LJST bit in the ADC0CN register must be
set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
0
GAINEN Gain Enable Bit.
Controls the gain programming. Refer to Section “6.3. Selectable Gain” on page 58
for information about using this bit.
Rev. 1.1
63
SILICON [ SILICON ]
