C8051F50x-F51x
Gain Register Definition 6.1. ADC0GNH: ADC0 Selectable Gain High Byte
Bit
7
6
5
4
3
2
1
0
GAINH[7:0]
Name
Type
Reset
W
1
1
1
1
1
1
0
0
Indirect Address = 0x04;
Bit Name
7:0 GAINH[7:0]
Function
ADC0 Gain High Byte.
See Section 6.3.1 for details on calculating the value for this register.
Note: This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
Gain Register Definition 6.2. ADC0GNL: ADC0 Selectable Gain Low Byte
Bit
7
6
5
4
3
2
1
0
GAINL[3:0]
Reserved Reserved Reserved Reserved
Name
Type
Reset
W
W
0
W
0
W
0
W
0
0
0
0
0
Indirect Address = 0x07;
Bit Name
7:4 GAINL[3:0]
Function
ADC0 Gain Lower 4 Bits.
See Figure 6.3.1 for details for setting this register.
This register is only accessed indirectly through the ADC0H and ADC0L register.
Reserved Must Write 0000b
3:0
Note: This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
Rev. 1.1
61
SILICON [ SILICON ]
