C8051F50x-F51x
Gain Register Definition 6.3. ADC0GNA: ADC0 Additional Selectable Gain
Bit
7
6
5
4
3
2
1
0
Reserved Reserved Reserved Reserved Reserved Reserved Reserved GAINADD
Name
Type
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
1
Indirect Address = 0x08;
Bit
7:1
0
Name
Function
Reserved Must Write 0000000b.
GAINADD ADC0 Additional Gain Bit.
Setting this bit add 1/64 (0.016) gain to the gain value in the ADC0GNH and
ADC0GNL registers.
Note: This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
62
Rev. 1.1