C8051F50x-F51x
SFR Definition 17.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
PINRSF
R
Name
Type
Reset
FERROR C0RSEF
SWRSF WDTRSF MCDRSF
PORSF
R/W
R
0
R
R/W
R/W
R
R/W
Varies
Varies
Varies
Varies
Varies
Varies
Varies
SFR Address = 0xEF; SFR Page = 0x00
Bit
Name
Description
Write
Read
7
Unused Unused.
Don’t care.
N/A
0
6
FERROR Flash Error Reset Flag.
Set to 1 if Flash
read/write/erase error
caused the last reset.
5
4
3
2
C0RSEF Comparator0 Reset Enable Writing a 1 enables
Set to 1 if Comparator0
caused the last reset.
and Flag.
Comparator0 as a reset
source (active-low).
SWRSF Software Reset Force and
Writing a 1 forces a sys-
tem reset.
Set to 1 if last reset was
caused by a write to
SWRSF.
Flag.
WDTRSF Watchdog Timer Reset Flag. N/A
Set to 1 if Watchdog Timer
overflow caused the last
reset.
MCDRSF Missing Clock Detector
Writing a 1 enables the
Missing Clock Detector.
Set to 1 if Missing Clock
Detector timeout caused
Enable and Flag.
The MCD triggers a reset the last reset.
if a missing clock condition
is detected.
1
PORSF Power-On/V Monitor
Writing a 1 enables the
DD monitor as a reset
source.
Set to 1 anytime a power-
on or VDD monitor reset
occurs.
DD
V
Reset Flag, and V monitor
DD
Reset Enable.
Writing 1 to this bit
When set to 1 all other
before the V monitor RSTSRC flags are inde-
DD
is enabled and stabilized terminate.
may cause a system
reset.
0
PINRSF HW Pin Reset Flag.
N/A
Set to 1 if RST pin caused
the last reset.
Note: Do not use read-modify-write operations on this register
146
Rev. 1.1
SILICON [ SILICON ]
