C8051F50x-F51x
17.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin is driven low until VDD settles above
VRST. A delay occurs before the device is released from reset; the delay decreases as the VDD ramp time
increases (VDD ramp time is defined as how fast VDD ramps from 0 V to VRST). Figure 17.2. plots the
power-on and VDD monitor reset timing.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a
power-on reset.
VDD
2.45
2.25
VRST
2.0
1.0
t
/RST
Logic HIGH
TPORDelay
Logic LOW
VDD
Power-On
Reset
Monitor
Reset
Figure 17.2. Power-On and VDD Monitor Reset Timing
17.2. Power-Fail Reset/V Monitor
DD
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 17.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The VDD
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the VDD monitor is disabled by code and a software reset is performed, the
VDD monitor will still be disabled after the reset. To protect the integrity of Flash contents, the V
DD
monitor must be enabled to the higher setting (VDMLVL = 1) and selected as a reset source if soft-
ware contains routines which erase or write Flash memory. If the V monitor is not enabled and
DD
set to the high level, any erase or write performed on Flash memory will cause a Flash Error device
reset.
142
Rev. 1.1
SILICON [ SILICON ]
