C8051F50x-F51x
Important Note: If the VDD monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the VDD monitor as a reset source before it is enabled and stabi-
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the VDD monitor and configuring it as a reset source from a disabled
state is as follows:
1. Enable the VDD monitor (VDMEN bit in VDM0CN = 1).
2. If necessary, wait for the VDD monitor to stabilize (see Table 5.4 for the VDD Monitor turn-on time).
Note: This delay should be omitted if software contains routines that erase or write Flash
memory.
3. Select the VDD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 17.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD
monitor reset. See Table 5.4 for complete electrical characteristics of the VDD monitor.
See “Figure 5.1. Minimum VDD Monitor Threshold vs. System Clock Frequency” on page 44 for VDD mon-
itor threshold level requirements.
Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset event. The
output of the un-calibrated internal regulator could be below the high threshold setting of the VDD Monitor. If
this is the case and the VDD Monitor is set to the high threshold setting and if the MCU receives a non-power
on reset (POR), the MCU will remain in reset until a POR occurs (i.e., VDD Monitor will keep the device in
reset). A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the un-
calibrated output of the internal regulator. The device will then exit reset and resume normal operation. It is for
this reason Silicon Labs strongly recommends that the VDD Monitor is always left in the low threshold setting
(i.e., default value upon POR).
When programming the Flash in-system, the VDD Monitor must be set to the high threshold setting. For the
highest system reliability, the time the VDD Monitor is set to the high threshold setting should be minimized
(e.g. setting the VDD Monitor to the high threshold setting just before the Flash write operation and then
changing it back to the low threshold setting immediately after the Flash write operation).
Rev. 1.1
143
SILICON [ SILICON ]
