C8051F50x-F51x
SFR Definition 17.1. VDM0CN: V Monitor Control
DD
Bit
7
6
5
4
3
2
1
0
VDMEN VDDSTAT VDMLVL
Name
Type
Reset
R/W
R
R/W
0
R
0
R
0
R
0
R
0
R
0
Varies
Varies
SFR Address = 0xFF; SFR Page = 0x00
Bit
Name
Function
7
VDMEN
V
Monitor Enable.
DD
This bit turns the VDD monitor circuit on/off. The VDD Monitor cannot generate sys-
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 17.2). Selecting the VDD monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the VDD Monitor and selecting it as a
reset source. See Table 5.4 for the minimum VDD Monitor turn-on time.
0: VDD Monitor Disabled.
1: VDD Monitor Enabled.
6
5
VDDSTAT
VDMLVL
Unused
V
Status.
DD
This bit indicates the current power supply status (VDD Monitor output).
0: VDD is at or below the VDD monitor threshold.
1: VDD is above the VDD monitor threshold.
V
Monitor Level Select.
DD
0: VDD Monitor Threshold is set to VRST-LOW
1: VDD Monitor Threshold is set to VRST-HIGH. This setting is required for any sys-
tem includes code that writes to and/or erases Flash.
4:0
Read = 00000b; Write = Don’t care.
17.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 5.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
17.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the value specified in Table 5.4, “Reset Electrical Characteristics,”
on page 46, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RST-
SRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the
MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is unaf-
fected by this reset.
144
Rev. 1.1
SILICON [ SILICON ]
