C8051F39x/37x
SFR Definition 9.1. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
AD0SC[4:0]
AD0LJST
Name
Type
Reset
R/W
1
R/W
0
R/W
1
1
1
1
0
0
SFR Address = 0xBC; SFR Page = All Pages
Bit
Name
Function
7:3
AD0SC[4:0]
ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from system clock by the fol-
lowing equation, where AD0SC refers to the 5-bit value held in
bits AD0SC4–0. SAR Conversion clock requirements are given
in the ADC specification Table 7.10.
SYSCLK
AD0SC = ----------------------- – 1
CLKSAR
2
AD0LJST
Reserved
ADC0 Left Justify Select.
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
1:0
Must Write 00b.
Preliminary Rev. 0.71
53
SILICON [ SILICON ]
