C8051F360/1/2/3/4/5/6/7/8/9
8. Comparators
C8051F36x devices include two on-chip programmable voltage comparators, Comparator0 and
Comparator1, shown in Figure 8.1 and Figure 8.2 (Note: the port pin Comparator inputs differ between
C8051F36x devices. The first Port I/O pin shown is for C8051F360/3 devices).
The comparators offer programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0 and CP1), or an
asynchronous “raw” output (CP0A and CP1A). The asynchronous CP0A and CP1A signals are available
even when the system clock is not active. This allows the Comparators to operate and generate an output
with the device in STOP mode. When assigned to a Port pin, the Comparator outputs may be configured
as open drain or push-pull (see Section “17.2. Port I/O Initialization” on page 187). Comparator0 may also
be used as a reset source (see Section “12.5. Comparator0 Reset” on page 131).
The Comparator inputs are selected in the CPT0MX and CPT1MX registers (SFR Definition 8.2 and SFR
Definition 8.5). The CMXnP1–CMXnP0 bits select the Comparator positive input; the CMXnN1–CMXnN0
bits select the Comparator negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be con-
figured as analog inputs in their associated Port configuration register, and configured to be skipped by the
Crossbar (for details on Port configuration, see Section “17.3. General Purpose Port I/O” on page 190).
CP0EN
CP0OUT
CP0RIF
CP0FIF
VDD
CMX0N3
CMX0N2
CMX0N1
CMX0N0
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CMX0P1
CMX0P0
P1.4 / P1.0
P2.3 / P1.4
P3.1 / P2.0
P3.5 / P2.4
CP0 +
CP0
+
-
SET
CLR
SET
CLR
D
Q
Q
D
Q
Q
Crossbar
(SYNCHRONIZER)
GND
CP0A
Reset
Decision
Tree
P1.5 / P1.1
P2.4 / P1.5
P3.2 / P2.1
P3.6 / P2.5
0
1
CP0
Interrupt
CP0EN
EA
CP0 -
CP0RIF
CP0FIF
0
0
1
1
0
1
CP0RIE
CP0FIE
CP0MD1
CP0MD0
Figure 8.1. Comparator0 Functional Block Diagram
70
Rev. 1.0
SILICON [ SILICON ]
