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C8051F363 参数 Datasheet PDF下载

C8051F363图片预览
型号: C8051F363
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 288 页 / 2659 K
品牌: SILICON [ SILICON ]
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C8051F360/1/2/3/4/5/6/7/8/9  
complete Port I/O configuration details. The TEMPE bit in register REF0CN enables/disables the tempera-  
ture sensor. While disabled, the temperature sensor defaults to a high impedance state and any ADC0  
measurements performed on the sensor result in meaningless data.  
SFR Definition 7.1. REF0CN: Reference Control  
SFR Page:  
all pages  
SFR Address: 0xD1  
R
R
R
R
R/W  
REFSL  
Bit3  
R/W  
TEMPE  
Bit2  
R/W  
BIASE  
Bit1  
R/W  
Reset Value  
Bit7  
REFBE 00000000  
Bit0  
Bit6  
Bit5  
Bit4  
Bits 7–4: UNUSED. Read = 0000b; Write = don’t care.  
Bit 3:  
REFSL: Voltage Reference Select.  
This bit selects the source for the internal voltage reference.  
0: VREF pin used as voltage reference.  
1: V used as voltage reference.  
DD  
Bit 2:  
Bit 1:  
Bit 0:  
TEMPE: Temperature Sensor Enable Bit.  
0: Internal Temperature Sensor off.  
1: Internal Temperature Sensor on.  
BIASE: Internal Analog Bias Generator Enable Bit.  
0: Internal Bias Generator off.  
1: Internal Bias Generator on.  
REFBE: Internal Reference Buffer Enable Bit.  
0: Internal Reference Buffer disabled.  
1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin.  
68  
Rev. 1.0  
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