C8051F360/1/2/3/4/5/6/7/8/9
CP1EN
CP1OUT
CP1RIF
VDD
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CMX1N1
CMX1N0
CMX1P1
CMX1P0
P2.0 / P1.2
P2.5 / P1.6
P3.3 / P2.2
P3.7 / P2.6
CP1 +
CP1
+
SET
CLR
SET
CLR
D
Q
Q
D
Q
Q
-
Crossbar
(SYNCHRONIZER)
GND
CP1A
P2.1 / P1.3
P2.6 / P1.7
P3.4 / P2.3
P4.0 / P2.7
0
1
CP1
Interrupt
CP1EN
EA
CP1 -
CP1RIF
CP1FIF
0
0
1
1
0
1
CP1RIE
CP1FIE
CP1MD1
CP1MD0
Figure 8.2. Comparator1 Functional Block Diagram
A Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin.
When routed to a Port pin, the Comparator outputs are available asynchronous or synchronous to the sys-
tem clock; the asynchronous outputs are available even in STOP mode (with no system clock active).
When disabled, the Comparator outputs (if assigned to a Port I/O pin via the Crossbar) default to the logic
low state, and their supply current falls to less than 100 nA. See Section “17.1. Priority Crossbar Decoder”
on page 185 for details on configuring Comparator outputs via the digital Crossbar. Comparator inputs can
be externally driven from –0.25 V to (V ) + 0.25 V without damage or upset. The complete Comparator
DD
electrical specifications are given in Table 8.1.
The Comparator response time may be configured in software via the CPT0MD and CPT1MD registers
(see SFR Definition 8.3 and SFR Definition 8.6). Selecting a longer response time reduces the Comparator
supply current. See Table 8.1 for complete timing and power consumption specifications.
Rev. 1.0
71
SILICON [ SILICON ]
