C8051F360/1/2/3/4/5/6/7/8/9
Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
PWM16 ECOM CAPP CAPN MAT TOG PWM ECCF
Operation Mode
Capture triggered by positive edge on
CEXn
X
X
X
X
X
X
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
X
X
X
Capture triggered by negative edge on
CEXn
Capture triggered by transition on
CEXn
X
X
X
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
X
X
X
0
Software Timer
High Speed Output
Frequency Output
8-Bit Pulse Width Modulator
16-Bit Pulse Width Modulator
1
0
X = Don’t Care
22.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic ‘1’ and an interrupt request is generated if CCF interrupts are enabled. The
CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine,
and must be cleared by software. If both CAPPn and CAPNn bits are set to logic ‘1’, then the state of the
Port pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge
caused the capture.
PCA Interrupt
PCA0CPMn
PCA0CN
P
W
M
1
E C C M T
C A A A O
O P P T G
M P N n n
n n n
P
W
M
n
E
C
C
F
n
C C C C C C C C
F R C C C C C C
F F F F F F
5 4 3 2 1 0
6
n
PCA0CPLn
PCA0CPHn
0
1
CEXn
Capture
Port I/O
Crossbar
0
1
PCA
Timebase
PCA0L
PCA0H
Figure 22.4. PCA Capture Mode Diagram
Note: The signal at CEXn must be high or low for at least 2 system clock cycles to be recognized by the
hardware.
Rev. 1.0
267
SILICON [ SILICON ]
