C8051F360/1/2/3/4/5/6/7/8/9
22. Programmable Counter Array
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. PCA0 consists of a dedicated 16-bit counter/timer and
six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled (See Section “17.3. General Pur-
pose Port I/O” on page 190). The counter/timer is driven by a programmable timebase that can select
between six inputs as its source: system clock, system clock divided by four, system clock divided by
twelve, the external oscillator clock source divided by 8, Timer 0 overflow, or an external clock signal on the
ECI line. Each capture/compare module may be configured to operate independently in one of six modes:
Edge-Triggered Capture, Software Timer, High-Speed Output, Frequency Output, 8-Bit PWM, or 16-Bit
PWM (each is described in Section 22.2). The PCA is configured and controlled through the system con-
troller's Special Function Registers. The basic PCA block diagram is shown in Figure 22.1.
Important Note: The PCA Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA registers is restricted while WDT mode is enabled.
See Section 22.3 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
PCA
16-Bit Counter/Timer
CLOCK
MUX
ECI
SYSCLK
External Clock/8
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Capture/Compare
Module 5
Crossbar
Port I/O
Figure 22.1. PCA Block Diagram
264
Rev. 1.0
SILICON [ SILICON ]
