C8051F360/1/2/3/4/5/6/7/8/9
22.2.3. High Speed Output Mode
In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn) Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPMn
Write to
PCA0CPHn
P
W
M
1
E C C M T
C A A A O
O P P T G
M P N n n
n n n
P
W
M
n
E
C
C
F
n
ENB
1
6
n
PCA
Interrupt
x
0 0
0 x
PCA0CN
C C C C C C C C
F R C C C C C C
F F F F F F
PCA0CPLn
PCA0CPHn
5 4 3 2 1 0
0
1
Enable
Match
16-bit Comparator
TOGn
Toggle
0
CEXn
Crossbar
Port I/O
1
PCA
Timebase
PCA0L
PCA0H
Figure 22.6. PCA High Speed Output Mode Diagram
Note: The initial state of the Toggle output is logic ‘1’ and is initialized to this state when the module enters
High Speed Output Mode.
Rev. 1.0
269
SILICON [ SILICON ]
