C8051F360/1/2/3/4/5/6/7/8/9
21.3. Timer 3
Timer 3 is a 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may
operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines
the Timer 3 operation mode.
Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. The external clock mode is ideal for real-time clock (RTC) functionality, where the
internal oscillator drives the system clock while Timer 3 (and/or the PCA) is clocked by an external preci-
sion oscillator. Note that the external oscillator source divided by 8 is synchronized with the system clock.
21.3.1. 16-bit Timer with Auto-Reload
When T3SPLIT (TMR3CN.3) is zero, Timer 3 operates as a 16-bit timer with auto-reload. Timer 3 can be
clocked by SYSCLK, SYSCLK divided by 12, or the external oscillator clock source divided by 8. As the
16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit value in the Timer 3
reload registers (TMR3RLH and TMR3RLL) is loaded into the Timer 3 register as shown in Figure 21.6,
and the Timer 3 High Byte Overflow Flag (TMR3CN.7) is set. If Timer 3 interrupts are enabled (if EIE1.7 is
set), an interrupt will be generated on each Timer 3 overflow. Additionally, if Timer 3 interrupts are enabled
and the TF3LEN bit is set (TMR3CN.5), an interrupt will be generated each time the lower 8 bits (TMR3L)
overflow from 0xFF to 0x00.
CKCON
T T T T T T S S
3 3 2 2 1 0 C C
M M M M M M A A
T3XCLK
H L H L
1 0
To ADC
SYSCLK / 12
0
1
0
1
TCLK
TR3
TF3H
TF3L
TF3LEN
TF3CEN
T3SPLIT
TR3
TMR3L
TMR3H
Interrupt
External Clock / 8
SYSCLK
T3XCLK
TMR3RLL TMR3RLH
Reload
Figure 21.6. Timer 3 16-Bit Mode Block Diagram
260
Rev. 1.0
SILICON [ SILICON ]
