C8051F360/1/2/3/4/5/6/7/8/9
1.2. On-Chip Memory
The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data
RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general
purpose RAM, and direct addressing accesses the 128 byte SFR address space. The lower 128 bytes of
RAM are accessible via direct and indirect addressing. The first 32 bytes are addressable as four banks of
general purpose registers, and the next 16 bytes can be byte addressable or bit addressable.
Program memory consists of 32/16 kB of Flash. This memory may be reprogrammed in-system in 1024
byte sectors, and requires no special off-chip programming voltage. See Figure 1.6 for the MCU system
memory map.
PROGRAM MEMORY
C8051F360/1/2/3/4/5/6/7
RESERVED
DATA MEMORY
INTERNAL DATA ADDRESS SPACE
0xFF
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
0x80
0x7F
0x7C00
0x7BFF
(Direct and Indirect
Addressing)
Lower 128 RAM
(Direct and Indirect
Addressing)
0x30
0x2F
FLASH
Bit Addressable
(In-System
Programmable in 1024
Byte Sectors)
0x20
0x1F
General Purpose
Registers
0x00
0x0000
EXTERNAL DATA ADDRESS SPACE
C8051F368/9
RESERVED
0xFFFF
0x4000
0x3FFF
Same 1024 bytes as from
0x0000 to 0x03FF, wrapped
on 1024-byte boundaries
FLASH
(In-System
Programmable in 1024
Byte Sectors)
0x0400
0x03FF
XRAM - 1024 Bytes
(accessable using MOVX
instruction)
0x0000
0x0000
Figure 1.6. On-Board Memory Map
1.3. On-Chip Debug Circuitry
The C8051F36x devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intru-
sive, full speed, in-circuit debugging of the production part installed in the end application.
Silicon Labs' debugging system supports inspection and modification of memory and registers, break-
points, and single stepping. No additional target RAM, program memory, timers, or communications chan-
24
Rev. 1.0
SILICON [ SILICON ]
