C8051F360/1/2/3/4/5/6/7/8/9
C2D
Port I/O Configuration
Debug / Programming
Hardware
P0.0/VREF
P0.1/IDA0
P0.2/XTAL1
C2CK/RST
Port 0
P0.3/XTAL2
Drivers
Digital Peripherals
Reset
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
CIP-51 8051
Controller Core
UART0
Power-On
Reset
Timers 0, 1,
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
2, 3
32/16 kB ISP FLASH
Program Memory
Priority
Port 1
Drivers
Supply
Monitor
Crossbar
Decoder
PCA/WDT
VDD
256 Byte RAM
1 kB XRAM
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
SMBus
SPI
Port 2
Drivers
Crossbar Control
SFR
Bus
GND
2-cycle 16 by 16 Multiply
and Accumulate
P3.0/C2D
P3.1
P3.2
P3.3
P3.4
Port 3
Drivers
System Clock Setup
Analog Peripherals
XTAL1
XTAL2
CP0
CP1
External
+
-
Oscillator
VREF
Clock
P0.1
10-bit
IDAC
+
-
Multiplier
Internal
Oscillator
2 Comparators
VDD
VREF
AIN0–AIN20
VDD
Low Frequency Oscillator
A
10-bit
200 ksps
ADC
M
U
X
Temp
Sensor
C8051F361/6/8 only
Figure 1.2. C8051F361/4/6/8 Block Diagram
C2D
Port I/O Configuration
Debug / Programming
P0.0/VREF
Hardware
C2CK/RST
P0.1/IDA0
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Port 0
Drivers
Digital Peripherals
Reset
CIP-51 8051
Controller Core
UART0
Power-On
Reset
Timers 0, 1,
2, 3
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
32/16 kB ISP FLASH
Program Memory
Priority
Crossbar
Decoder
Port 1
Drivers
Supply
Monitor
PCA/WDT
VDD
256 Byte RAM
1 kB XRAM
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
SMBus
SPI
Port 2
Drivers
SFR
Bus
Crossbar Control
GND
2-cycle 16 by 16 Multiply
and Accumulate
Port 3
Drivers
P3.0/C2D
System Clock Setup
Analog Peripherals
CP0
CP1
+
-
XTAL1
XTAL2
External
VREF
P0.1
10-bit
IDAC
Oscillator
+
-
Clock
Multiplier
Internal
2 Comparators
VDD
VREF
Oscillator
AIN0–AIN20
VDD
A
10-bit
200 ksps
ADC
Low Frequency Oscillator
M
U
X
Temp
Sensor
C8051F362/7/9 only
Figure 1.3. C8051F362/5/7/9 Block Diagram
Rev. 1.0
21
SILICON [ SILICON ]
