C8051F360/1/2/3/4/5/6/7/8/9
C2D
Port I/O Configuration
Debug / Programming
Hardware
P0.0
P0.1/TX
C2CK/RST
P0.2/RX
Port 0
Drivers
P0.3/VREF
P0.4/IDA0
P0.5/XTAL1
P0.6/XTAL2
P0.7/CNVSTR
Digital Peripherals
Reset
CIP-51 8051
UART0
Power-On
Reset
Controller Core
Timers 0, 1,
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
2, 3
32/16 kB ISP FLASH
Program Memory
Priority
Crossbar
Decoder
Port 1
Drivers
Supply
Monitor
PCA/WDT
VDD
256 Byte RAM
1 kB XRAM
Power
Net
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
SMBus
SPI
Port 2
Drivers
Crossbar Control
GND
2-cycle 16 by 16 Multiply
and Accumulate
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
External Memory
Interface
SFR
Bus
Port 3
Drivers
P0 / P4
System Clock Setup
Control
Address
Data
XTAL1
XTAL2
External
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6/C2D
P2 / P3 / P4
P1
Oscillator
Clock
Port 4
Drivers
Multiplier
Internal
Oscillator
Low Frequency Oscillator
Analog Peripherals
CP0
CP1
+
-
VREF
P4.4
10-bit
IDAC
+
-
2 Comparators
VDD
VREF
AIN0–AIN16
VDD
A
10-bit
200 ksps
ADC
M
U
X
Temp
Sensor
C8051F360 only
Figure 1.1. C8051F360/3 Block Diagram
20
Rev. 1.0
SILICON [ SILICON ]
