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C8051F363 参数 Datasheet PDF下载

C8051F363图片预览
型号: C8051F363
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 288 页 / 2659 K
品牌: SILICON [ SILICON ]
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C8051F360/1/2/3/4/5/6/7/8/9  
18.6. SMBus Status Decoding  
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS  
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown  
response options are only the typical responses; application-specific procedures are allowed as long as  
they conform to the SMBus specification. Highlighted responses are allowed but do not conform to the  
SMBus specification.  
Table 18.4. SMBus Status Decoding  
Values  
Written  
Values Read  
Current SMbus State  
Typical Response Options  
Load slave address + R/W  
into SMB0DAT.  
0
0
X
1110  
1100  
0
0
0
0
X A master START was generated.  
Set STA to restart transfer.  
Abort transfer.  
1
0
0
0
1
0
X
X
X
A master data or address byte  
was transmitted; NACK received.  
0
Load next data byte into  
SMB0DAT.  
End transfer with STOP.  
0
1
1
1
X
X
End transfer with STOP and  
start another transfer.  
A master data or address byte  
was transmitted; ACK received.  
0
0
1
Send repeated START.  
1
0
0
0
X
X
Switch to Master Receiver  
Mode (clear SI without writ-  
ing new data to SMB0DAT).  
Rev. 1.0  
217  
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