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SAB82525H-V21 参数 Datasheet PDF下载

SAB82525H-V21图片预览
型号: SAB82525H-V21
PDF下载: 下载PDF文件 查看货源
内容描述: 高层次的串行通信控制器扩展 [High-Level Serial Communication Controller Extended]
分类和应用: 通信控制器
文件页数/大小: 126 页 / 741 K
品牌: SIEMENS [ Siemens Semiconductor Group ]
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SAB 82525  
SAB 82526  
SAF 82525  
SAF 82526  
4.5 FIFO Structure  
In both transmit and receive direction 64-byte deep FIFO’s are provided for the intermediate  
storage of data between the serial interface and the CPU interface. The FIFO’s are divided into  
two halves of 32-bytes, where only one half is accessible to the CPU or DMA controller at any  
time.  
The organization of the Receive FIFO (RFIFO) is such, that in the case of a frame at most 64  
bytes long, the whole frame may be stored in the RFIFO. After the first 32 bytes have been  
received, the HSCX prompts to read the 32-byte block by means of interrupt or DMA request  
(RPF interrupt or activation of DRQR line). This block remains in the RFIFO until a confirmation  
is given to the HSCX acknowledging the transfer of the data block. This confirmation is either  
a RMC (Receive Message Complete) command via the CMDR register in Interrupt Mode, or  
is implicitly achieved in DMA mode after 32-bytes have been read from the RFIFO. As a result,  
it’s possible in Interrupt Mode, to read out the data block any number of times until the RMC  
command is issued.  
The configuration of the RFIFO prior to and after acknowledgement is shown in figure 21.  
32 Bytes  
Inaccessible  
Free  
Block  
B + 1  
32 Bytes  
Accessible  
Block  
B
Block  
B + 1  
a) Prior to  
b) After  
Acknowledgement  
Acknowledgement  
ITD01582  
Figure 21  
Configuration of RFIFO (Long Frames)  
Semiconductor Group  
47  
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