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SAB82525H-V21 参数 Datasheet PDF下载

SAB82525H-V21图片预览
型号: SAB82525H-V21
PDF下载: 下载PDF文件 查看货源
内容描述: 高层次的串行通信控制器扩展 [High-Level Serial Communication Controller Extended]
分类和应用: 通信控制器
文件页数/大小: 126 页 / 741 K
品牌: SIEMENS [ Siemens Semiconductor Group ]
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SAB 82525  
SAB 82526  
SAF 82525  
SAF 82526  
T1  
T2  
T3  
T4  
T1  
T2  
T3  
T4  
CLOCKOUT  
DRQ  
RD  
(Memory)  
WR  
(FIFO)  
ITD02698  
tCVCTV  
tINVCL  
tDRHSYS  
tDRHSYS  
max = T2 - tCVCTV - tINVCL  
fCLKOUT  
tCLCL  
tCVCTV  
tINVCL  
tDRHSYS  
max  
8 MHz  
125 ns  
80 ns  
56 ns  
47 ns  
31ns  
15 ns  
15 ns  
15 ns  
54 ns  
18 ns  
12.5 MHz  
16 MHz  
62.5 ns  
16.5 ns  
If you use the write signal instead of the chip select signal in order to reset the DMA request  
you gain some time. The extra circuit is just an AND gate. The first input of the AND gate is  
connected to the DMA request line of the peripheral IC; the second input is connected to the  
chip select line. The AND gate’s output is the DMA request signal for the 80(C)188.  
&
DRQTx  
CS  
DRQ  
PCS  
80(C)188  
HSCX  
ITS02699  
Theoretically, the request line of an 80(C)188, for example, would still be active when the de-  
termination is made and DMA cycles would be performed permanently. Therefore the decision  
of the DMA request line is delayed; it is already made two clock cycles before the end of the  
write cycle. If no wait-states are inserted the decision is made at the end of the T2 clock cycle.  
Due to the fact that the write signal will be valid at the beginning of T2 there is only little time  
left for resetting the DMA request line.  
Semiconductor Group  
45  
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