SAB 82525
SAB 82526
SAF 82525
SAF 82526
Clock Mode 1 (Receive/Transmit Strobes)
Externally generated, but identical receive and transmit clocks are forwarded via R × CLK pins.
In addition, a receive strobe can be connected via A×CLK and a transmit strobe via T × CLK
pins. The operating mode can be applied in time division multiplex applications or for adjusting
disparate transmit and receive data rates.
Clock Mode 2 (Receive Clock from DPLL)
The BRG is driven with an external clock (R × CLK) and it delivers a reference clock for the
DPLL which in turn generate the receive clock. Depending on the programming of the CCR2
register (TSS bit), the transmit clock will be either an external clock signal (T× CLK) or the clock
delivered by the BRG divided by 16. In this case, the transmit clock can be output via T × CLK
(CCR2 : TIO = 1).
Clock Mode 3 (Receive and Transmit Clock from DPLL)
The BRG is fed with an externally generated clock via R× CLK and supplies the reference clock
for DPLL, which generates both the receive and transmit clock. This clock can also be output
via T × CLK pin.
Clock Mode 4 (OSC-Direct)
The receive and transmit clocks are directly supplied by the OSC. In addition this clock can
be output via T × CLK.
Clock Mode 5 (Time-Slots)
This operating mode has been designed for application in time-slot oriented PCM systems.
The receive and transmit clock is identical for each channel and must be supplied externally
via R × CLK pins. The HSCX receives and transmits only during certain time-slots of
programmable width (1. . .256 bit, via RCCR and XCCR registers) and location with respect to
a frame synchronization signal, which must be delivered to the HSCX via the
A × CLK pin. One of up to 64 time-slots can be programmed independently for receive and
transmit direction via TSAR and TSAX registers, and an additional clock shift of 0…7 bits via
TSAR, TSAX, and CCR2 registers. Together with bits XCS0 and RCS0 (LSB of clock shift),
located in the CCR2 register, there are 9 bits to determine the location of a time-slot.
According to the value programmed via those bits, the receive/transmit window (time-slot)
starts with a delay of 1 (minimum delay) up to 512 clock periods following the frame
synchronization signal and is active during the number of clock periods programmed via
RCCR, XCCR (number of bits to be received/transmitted within a time-slot) as shown in
figure 23.
Semiconductor Group
50
SIEMENS [ Siemens Semiconductor Group ]
