LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
NOTES:
1. RA can be the GSR address or any BSR address. See Figure 5 and 6 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the actual lock-
bit status.
3. A is automatically complemented to load second byte of data. BYT» E» must be at V . A value determines which WD/BC is supplied
0
IL
0
first: A = 0 looks at the WDL/BCL, A = 1 looks at the WDH/BCH.
0
0
4. BCH/WCH must be at 00H for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the Page Buffer
contents into more than one 256-Byte segment within an array block. They are simply shown for future Page Buffer expandability.
5. In x16 mode, only the lower byte DQ - DQ is used for WCL and WCH. The upper byte DQ - DQ is a don’t care.
0
7
8
15
6. PA and PD (Whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY»/BY» output to one of two pulse-modes or enable and disable the RY»/BY» function.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the
LH28F800SU User’s Manual.
10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1.
Compatible Status Register
WSMS
7
ESS
6
ES
5
DWS
4
VPPS
3
R
2
R
1
R
0
NOTES:
CSR.7
=
=
=
=
=
WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
1. RY»/BY» output or WSMS bit must be checked to determine
completion of an operation (Erase Suspend, Erase or Data
Write) before the appropriate Status bit (ESS, ES or DWS)
is checked for success.
CSR.6
CSR.5
CSR.4
CSR.3
ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase in Progress/Completed
2. If DWS and ES are set to ‘1’ during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
3. The VPPS bit, unlike an A/D converter, does not provide
continuous indication of V level. The WSM interrogates
PP
V
’s level only after the Data-Write or Erase command
PP
sequences have been entered, and informs the system if
has not been switched on. VPPS is not guaranteed to
DATA-WRITE STATUS (DWS)
1 = Error in Data Write
0 = Data Write Successful
V
PP
report accurate feedback between V
and V
.
PPL
PPH
4. CSR.2 - CSR.0 = Reserved for future enhancements.
These bits are reserved for future use and should be
masked out when polling the CSR.
V
STATUS (VPPS)
PP
1 = V Low Detect, Operation Abort
PP
0 = V OK
PP
12
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
